Field
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of the plurality of inputs to provide an output.
Description
It is known to provide arbitrating and multiplexing circuitry. One known form of arbitrating and multiplexing circuitry is as illustrated in FIG. 1 of the accompanying drawings. In this example, an arbiter 2 is disposed in series with a multiplexer 4. The arbiter 2 receives a plurality of requests indicating which inputs are carrying data between which an arbitration is required. The arbiter 2 performs an arbitration in accordance with whatever arbitration algorithm is being employed, and generates a grant signal to select one of the inputs. The grant signal is supplied to the multiplexer 4 and controls the multiplexer 4 to select the appropriate input to serve as the output from the multiplexer 4. The processing delay associated with the action of the circuitry of FIG. 1 is at least the time taken for the arbiter 2 to perform the arbitration operation summed with the time taken for the multiplexer 4 to perform the selection operation in response to the grant signal generated by the arbiter 2 after it has finished its arbitration.
The time taken for the serially performed arbitration and multiplexing operations of the circuitry of FIG. 1 may be a limitation in system performance, e.g. may limit clock frequency and/or require the operation to be spread over multiple clock cycles in a manner which increases latency, etc.